Phase Noise Budget — Cascaded System Specification Allocation

1. Introduction

Every complex RF system is a chain of components. A reference oscillator feeds a frequency multiplier, which drives a filter, which buffers an amplifier, which reaches the output. Each stage adds its own phase noise. The question is not whether these noise contributions accumulate—they do—but how they combine and how you allocate system-level specifications across the chain.

Phase noise budgeting is the systematic process of distributing phase noise specifications across cascaded components to ensure the final system meets its jitter and spectral purity requirements. Without a rigorous budget, you risk either over-specifying components (driving up cost unnecessarily) or under-specifying them (resulting in system-level failure).

This application note covers:

• The fundamental reason system-level budgeting differs from component-level characterization
• The cascaded noise addition principle and its mathematical foundation
• A step-by-step budgeting methodology that starts from system jitter requirements
• A detailed 5-stage cascaded example: Reference → Splitter → Multiplier → Filter → Output
• Cross-verification using the BRIDZA Phase Noise Budget Calculator
• Common pitfalls and their solutions
• Optimization strategies for cost-effective system design

2. Why System-Level Phase Noise Budgeting Matters

2.1 Single-Component Specification vs. System Performance

Phase noise is typically measured on a single component in isolation—your oscillator datasheet shows a plot like Figure 1, with values at specific offset frequencies (1 Hz, 10 Hz, 100 Hz, 1 kHz, 10 kHz, 100 kHz, 1 MHz). This is the single-sideband phase noise L(f) in dBc/Hz.

However, when that oscillator is embedded in a system, it drives downstream stages. Each subsequent stage—multipliers, mixers, amplifiers, filters—adds its own phase noise. The system-level phase noise is the aggregate of all contributions, with the dominant contribution typically coming from the earliest stage in the chain (the reference) but modified by frequency-translation stages.

Consider a 5G base station clock chain: you select an OCXO with excellent phase noise at –140 dBc/Hz @ 10 kHz. But after a ×20 frequency multiplier, the near-carrier noise rises by 20·log₁₀(20) = 26 dB. After a clock buffer with 10 dB noise figure, the contribution is no longer negligible. Your "excellent" oscillator alone does not guarantee system performance.

2.2 The Cascaded Noise Addition Principle

For uncorrelated, non-coherent noise sources (which phase noise contributions from different stages generally are), power adds in a root-sum-square (RSS) fashion:

L_total(f_offset) = √(L₁² + L₂² + L₃² + ... + Lₙ²)

In decibel form:
L_total(dBc/Hz) = 10 × log₁₀(10^(L₁/10) + 10^(L₂/10) + 10^(L₃/10) + ... + 10^(Lₙ/10))

This is not the same as adding dB values directly (which would be correct only if all noise came from a single source). The RSS method ensures that the dominant noise contributor sets the floor, but other contributors can still degrade the total if they are within ~10 dB of the dominant source.

2.3 When You Need a Phase Noise Budget

Phase noise budgeting is essential whenever any of the following conditions apply:

• Communication systems with strict spectral mask requirements: LTE, 5G NR, Wi-Fi 6E, satellite communications. Phase noise translates directly into error vector magnitude (EVM) degradation and adjacent channel leakage ratio (ACLR) violations.
• Radar systems where phase noise manifests as elevated spurious responses and reduced detection sensitivity in clutter. Synthetic aperture radar (SAR) and phased array systems are particularly sensitive.
• Test and measurement instruments such as signal generators, spectrum analyzers, and frequency counters. The source phase noise determines the instrument's noise floor.
• Satellite payloads where on-board oscillators feed frequency conversion chains. In-space thermal cycling and radiation hardness requirements make budgeting critical.
• Any system with frequency multiplication or division: Multipliers amplify phase noise by 20·log₁₀(N), where N is the multiplication factor. This alone can invalidate a naive component selection.

3. Budgeting Methodology: From System Requirements to Component Allocations

3.1 Starting Point: System Jitter Requirement

Every phase noise budget begins with a system-level jitter specification. This is typically expressed as RMS jitter (in femtoseconds or picoseconds) over a defined integration band, or as a maximum acceptable RMS phase error for a specific communication standard.

For example, a 5G NR base station might require integrated RMS jitter < 200 fs over the 12 kHz to 20 MHz offset range (for LTE-A and NR FR1). A X-band radar might require < 1 ps RMS jitter integrated from 100 Hz to 1 MHz.

The first step is to translate this jitter requirement into a phase noise mask at the system output, then work backward to allocate that mask across the signal chain.

3.2 The Top-Down Budgeting Approach

The most effective methodology flows from output to input:

1. Define the system output jitter requirement (e.g., < 200 fs RMS over 12 kHz–20 MHz)
2. Convert jitter to a phase noise mask: This is the maximum L(f) the system output can exhibit at each offset frequency. Use the inverse relationship: integrating the mask over the band should yield the permitted jitter squared.
3. Account for frequency translation: If the output frequency differs from intermediate frequencies, map the mask back to the reference frequency using the multiplication/division factors.
4. Allocate the mask across stages: Each stage receives a portion of the total budget. The allocation can be equal (simplest), proportional to stage count (conservative), or weighted by stage criticality (most common in practice).
5. Verify with RSS combination: The RSS of all stage contributions must fall below the system mask.

3.3 Budget Allocation Principles

Not all stages are equal in their impact on system performance. The following principles guide intelligent budget allocation:

• Reference stage dominates: The reference oscillator typically sets the near-carrier noise floor. Allocate a tighter specification here than to downstream stages—this is the highest-leverage investment in the chain.
• Multiplication/division stages amplify noise: A ×N multiplier adds 20·log₁₀(N) dB to the phase noise at all offsets. Allocate a correspondingly tighter budget to the reference or add a cleaning PLL after multiplication.
• Non-critical stages can be relaxed: Buffer amplifiers and output stages that operate at the final frequency and do not feed sensitive downconversion can often tolerate higher phase noise contributions.
• Stage order matters: A noisy stage placed early in the chain (close to the reference) has more impact than the same stage placed near the output, because subsequent stages can amplify or filter its noise contribution.

4. Mathematics: Converting Phase Noise to Jitter

4.1 The Jitter Integration Formula

The RMS jitter (in radians) is obtained by integrating the phase noise spectrum L(f) over the specified offset frequency range:

σ_φ² (rad²) = 2 × ∫[f_min to f_max] L(f) df

Where:
  σ_φ² = variance of phase error in radians squared
  L(f) = single-sideband phase noise (in W/W, not dB)
  f = offset frequency from carrier
  f_min, f_max = integration band limits

RMS Jitter (seconds) = σ_φ / (2π × f_carrier)

The factor of 2 accounts for both sidebands (upper and lower). In practice, L(f) is measured in dBc/Hz and must be converted to linear form before integration:

L_linear(f) = 10^(L_dBc_Hz / 10)

4.2 Practical Integration Band Considerations

The integration band is determined by the specific application. Different communication standards and system types care about different offset ranges:

4.3 Worked Example: Jitter from Phase Noise Data

Given an oscillator with phase noise:

• 1 kHz offset: –120 dBc/Hz
• 10 kHz offset: –135 dBc/Hz
• 100 kHz offset: –145 dBc/Hz
• 1 MHz offset: –150 dBc/Hz

To estimate RMS jitter from 1 kHz to 1 MHz, we approximate the integral using piecewise constant segments:

Segment 1 (1 kHz – 10 kHz): L ≈ 10^(-120/10) = 1.0×10⁻¹²
  Contribution = 2 × 1.0×10⁻¹² × (10,000 – 1,000) = 1.8×10⁻⁸ rad²

Segment 2 (10 kHz – 100 kHz): L ≈ 10^(-135/10) = 3.16×10⁻¹⁴
  Contribution = 2 × 3.16×10⁻¹⁴ × (100,000 – 10,000) = 5.7×10⁻⁹ rad²

Segment 3 (100 kHz – 1 MHz): L ≈ 10^(-145/10) = 3.16×10⁻¹⁵
  Contribution = 2 × 3.16×10⁻¹⁵ × (1,000,000 – 100,000) = 5.7×10⁻⁹ rad²

Total σ_φ² ≈ (1.8 + 0.57 + 0.57) × 10⁻⁸ ≈ 2.9×10⁻⁸ rad²
σ_φ ≈ √(2.9×10⁻⁸) ≈ 5.4×10⁻⁴ rad ≈ 310 μrad

RMS Jitter @ 10 MHz = σ_φ / (2π × 10×10⁶)
  ≈ 5.4×10⁻⁴ / (6.28×10⁷) ≈ 8.6 ps

This is a coarse approximation. In practice, use the BRIDZA Phase Noise to Jitter Calculator which performs numerical integration across the full data series.

5. 5-Stage Cascaded System Example

Consider a typical timing distribution system operating at 100 MHz output:

Stage 1: Reference Oscillator (10 MHz OCXO)
Stage 2: Power Splitter (1:4)
Stage 3: Frequency Multiplier (×10)
Stage 4: Bandpass Filter
Stage 5: Output Buffer Amplifier

5.1 System Requirements

• Output frequency: 100 MHz
• Total RMS jitter: < 100 fs (12 kHz – 1 MHz integration)
• Phase noise mask at output: Must meet –100 dBc/Hz @ 1 kHz, –130 dBc/Hz @ 10 kHz, –145 dBc/Hz @ 100 kHz

5.2 Stage-by-Stage Analysis

Stage 1: Reference Oscillator (10 MHz OCXO)

Selected: High-stability OCXO with the following phase noise at 10 MHz:

Stage 2: Power Splitter (1:4)

A passive splitter introduces minimal additional phase noise. For a resistive or transformer-based splitter, the noise contribution is essentially the thermal noise floor of the termination resistances, which at room temperature is:

kTB (thermal noise) ≈ –174 dBm/Hz at 290 K
For a 0 dBm signal level: Noise Floor ≈ –174 dBc/Hz
This is negligible compared to our –100 to –140 dBc/Hz targets

Assigned budget contribution: –180 dBc/Hz (effectively negligible)

Stage 3: Frequency Multiplier (×10)

The ×10 multiplier amplifies the reference phase noise by 20·log₁₀(10) = 20 dB. The reference's 1 kHz noise of –125 dBc/Hz becomes –105 dBc/Hz at the multiplier output. Additionally, the multiplier itself introduces its own contribution, typically dominated by its internal VCO/PLL noise:

Multiplier noise contribution: approximately –130 dBc/Hz (input-referred, at 100 MHz)

Stage 4: Bandpass Filter

A crystal or SAW filter at 100 MHz contributes minimally phase noise. Its primary effect is to suppress spurious signals and out-of-band noise, which can indirectly improve the effective in-band noise floor.

Assigned budget contribution: –160 dBc/Hz (negligible)

Stage 5: Output Buffer Amplifier

A low-noise buffer amplifier adds its own noise, referred to its input and then scaled by the signal gain. For a buffer with 10 dB gain and 5 dB noise figure:

Input-referred noise = –174 + NF + 10×log₁₀(BW)
At 1 kHz bandwidth: ≈ –174 + 5 + 30 ≈ –139 dBm
Signal level at input: 0 dBm
Input-referred phase noise: ≈ –139 dBc/Hz

Assigned budget contribution: –140 dBc/Hz

5.3 Budget Summary Table

The RSS calculation shows that the dominant contributor is the multiplied reference (Stage 1 + Stage 3 multiplier self-noise). Stages 2, 4, and 5 contribute minimally—they are more than 20 dB below the dominant contributors.

6. Cross-Verification with Phase Noise Budget Calculator

The hand calculations above can be verified efficiently using the BRIDZA Phase Noise Budget Calculator. The tool accepts:

• Stage-by-stage phase noise data tables
• Frequency multiplication/division factors per stage
• Integration band definitions
• Noise addition model (RSS or direct power summation)

The calculator computes the cascaded phase noise at each offset, applies the multiplication factors, performs RSS combination, and outputs the total integrated RMS jitter. For the example above, the calculator confirms approximately 85 fs RMS jitter (12 kHz–1 MHz), providing 15% margin against the 100 fs requirement.

The slight discrepancy between hand calculation (≈8.6 ps for a simplified single-oscillator) and the cascaded result (85 fs) reflects the conservative nature of the hand approximation. Always use the calculator for final verification.

Try it yourself: Phase Noise Budget Calculator

7. Common Pitfalls in Phase Noise Budgeting

7.1 Ignoring Near-Carrier Noise Accumulation

The most common mistake is focusing only on the "knee" region (typically 1 kHz–100 kHz offsets) while neglecting offsets below 1 kHz. In a cascaded system, near-carrier noise from multiple stages can accumulate significantly, even if each stage appears quiet at higher offsets.

Example: A 5-stage system where each stage contributes –110 dBc/Hz @ 100 Hz. The RSS total is:

5 stages × 10^(-110/10) = 5 × 10^(-11) = 5×10⁻¹¹
L_total = 10×log₁₀(5×10⁻¹¹) = –113 dBc/Hz

Five stages each nominally "acceptable" at –110 dBc/Hz combine to –113 dBc/Hz, which may violate a tight near-carrier mask. Always budget for offsets down to 1 Hz, or at least 10 Hz, depending on your application.

7.2 Misapplying the 20·log(N) Multiplication Rule

The 20·log₁₀(N) rule applies only to phase noise that is coherent with the input signal. This is generally true for thermal noise-limited regions of the phase noise curve, but it breaks down in regions where the multiplier's internal circuitry dominates. Specifically:

• The rule is valid for offset frequencies where the input-referred noise of the multiplier (VCO, PLL, dividers) is below the multiplied reference noise.
• Near the carrier (< 1 kHz offsets for many PLLs), the multiplier's internal PLL loop bandwidth determines the actual noise, which may not scale as 20·log(N).
• Always check the multiplier datasheet for "output phase noise" specs rather than applying a simple scaling to input phase noise.

7.3 Confusing Temperature Drift with Phase Noise

System architects sometimes conflate two distinct phenomena:

• Phase noise: Rapid, stochastic frequency fluctuations about the carrier, characterized by spectral density L(f) in dBc/Hz. These are relevant for communication link budgets and radar clutter performance.
• Temperature-induced drift: Slow, deterministic frequency offset changes due to ambient temperature variations. This is characterized in ppb/°C or ppm/°C and is relevant for absolute frequency accuracy over time.

A system can have excellent phase noise but poor temperature stability, or vice versa. They require separate specifications and cannot be substituted for each other in the budget.

7.4 Neglecting Power Supply Noise Coupling

Phase noise specifications assume a clean power supply. In the real world, switching regulators, digital logic, and motor control circuits inject noise onto shared power rails. This noise, if coupled into the oscillator or multiplier supply, can modulate the carrier frequency and create "spurs" in the phase noise spectrum.

Mitigation strategies:

• Use low-noise LDOs with high PSRR (> 60 dB at 10 kHz) for oscillator and multiplier supplies
• Add LC or RC filters between the LDO and the sensitive RF stage
• Route power planes with adequate decoupling (10 µF + 100 nF + 1 nF per pin)
• Physically separate noisy digital circuits from sensitive RF stages

8. Optimization Strategies

8.1 Where to Invest for Maximum Return

Given a fixed total jitter budget, where should you spend the most money for the best system-level improvement? The answer is almost always: the reference oscillator.

Consider this analysis: improving the reference oscillator by 10 dB at 1 kHz offset reduces system jitter by approximately 10 dB (since the reference dominates). Improving a downstream buffer by 10 dB has minimal effect if the reference already sets the floor—the buffer contribution is buried 20+ dB below.

8.2 PLL Cleaning vs. Direct Low-Noise Source

When a system requires frequency multiplication, you have two architectural choices:

• Direct multiplication: Reference × N → Output. Simple, but the multiplied phase noise grows as 20·log(N). For N > 20, this becomes challenging.
• PLL-cleaned multiplication: Reference → PLL → VCO at target frequency. The PLL's loop bandwidth determines how much of the reference noise passes through. Outside the loop bandwidth, the VCO's own noise dominates. This can provide better near-carrier noise than direct multiplication, but requires careful PLL design.

For N = 10 to 100, PLL cleaning typically provides 10–20 dB improvement in the 1–100 kHz offset region compared to direct multiplication, at the cost of added complexity and potential for PLL-induced spurious signals.

8.3 Reference Source Selection Impact

The choice of reference source propagates through the entire budget. Here's how common reference types compare:

For the 5-stage example in Section 5, using a rubidium reference instead of the selected OCXO would provide an additional 10 dB margin at 1 kHz, or equivalently, allow a less stringent multiplier specification.

9. Conclusion

Phase noise budgeting for cascaded systems is not optional—it is a fundamental engineering discipline that separates successful designs from field failures. The key principles to remember:

• Start from system jitter requirements and work backward to component allocations. Never select components first and hope they meet requirements.
• Use RSS for noise combination: uncorrelated noise sources add in root-sum-square. Direct dB addition is only valid for a single dominant source.
• The reference dominates: invest the most effort and budget in the reference oscillator. Downstream stages matter, but the reference sets the ceiling.
• Account for frequency translation: multipliers amplify phase noise by 20·log(N). Cleaning PLLs can recover some of this degradation but add complexity.
• Verify with tools: use the BRIDZA Phase Noise Budget Calculator to cross-check hand calculations and catch errors before prototype.
• Consider real-world factors: power supply noise, thermal coupling, and near-carrier accumulation are common sources of budget overruns that are invisible in datasheet-only analysis.

The 5-stage example in this application note demonstrates that a well-budgeted system with a high-quality OCXO reference can achieve < 100 fs RMS jitter—even through a ×10 multiplier and multiple passive/active stages. The margin exists because the reference provides enough headroom to absorb downstream contributions.

For further reading and related tools:

• Phase Noise Budget Calculator — Model your cascaded system online
• Phase Noise to Jitter Calculator — Convert L(f) to RMS jitter
• AN-004: Phase Noise Measurement Techniques
• AN-011: 5G Clock Chain Design

For additional technical specifications, application support, or evaluation units, contact your BRIDZA representative.