⚡ Phase Noise Budget Calculator
Cascade your clock chain — oscillator, buffer, divider, PLL — and calculate total integrated phase noise, RMS jitter, and each stage's contribution.
What is a phase noise budget?
A phase noise budget analyzes the total phase noise contribution of each component in a clock chain (oscillator, buffer, divider, PLL) to ensure the system meets its jitter or phase noise requirements. It helps identify which component dominates the noise performance.
How do you calculate cascaded phase noise?
For uncorrelated noise sources (the typical case), total phase noise power adds linearly: L_total(f) = 10·log₁₀(Σ 10^(L_i(f)/10)). This assumes each stage adds independent noise. For correlated sources (e.g., the same oscillator through different paths), phase noise adds coherently (6 dB higher when two equal correlated sources combine).
How does a clock divider affect phase noise?
An ideal frequency divider reduces phase noise by 20·log₁₀(N) dB, where N is the division ratio. For example, dividing by 2 reduces phase noise by 6 dB. Real dividers add their own additive phase noise, typically -150 to -160 dBc/Hz at far-from-carrier offsets.
How does a clock buffer affect phase noise?
A clock buffer adds additive phase noise (close-in noise is typically dominated by the source; far-from-carrier noise is dominated by the buffer). Typical additive phase noise for a good clock buffer is -155 to -165 dBc/Hz at 10 kHz–10 MHz offsets. This adds to the source noise power-wise.
How to convert phase noise to jitter?
Integrate the single-sideband phase noise L(f) over the offset frequency range: Phase jitter (rad RMS) = √(2 · ∫ 10^(L(f)/10) df). Then: Time jitter = Phase jitter / (2π · f_carrier). This calculator performs the integration numerically using the trapezoidal rule.