PDRO Integration Guide

BRIDZA

Table of Contents

• Installation Requirements
• Reference Signal Input Configuration
• Phase Lock Status Monitoring
• RF Output Verification
• Troubleshooting

1. Installation Requirements

1.1 PDRO Module Overview

┌────────────────────────────────────────────────────────────┐
│ BRIDZA PDRO Module │
├────────────────────────────────────────────────────────────┤
│ │
│ REF INPUT MODULE BODY RF OUTPUT │
│ ┌────────┐ ┌──────────┐ ┌──────────┐ │
│ │ SMA │◄──────│ │─────────►│ SMA │ │
│ │ female│ │ HEATSINK│ │ female │ │
│ └────────┘ │ │ └──────────┘ │
│ │ [LOCK]│ │
│ D-SUB 9-pin │ LED │ STATUS: │
│ ┌────────┐ └──────────┘ ● PWR │
│ │ ◉◉◉◉◉ │ ● LOCK │
│ │ ◉◉◉◉ │ 95mm × 70mm × 25mm ○ ALM │
│ └────────┘ 
└────────────────────────────────────────────────────────────┘

1.2 Environmental Requirements

1.3 Thermal Management

Critical: PDRO modules generate significant heat during operation.

Heatsink Requirements:

Thermal Interface Material (TIM):

• Use thermal pad or compound between module and heatsink
• Recommended: Bergquist GPV-35 or equivalent
• Thickness: 0.5mm (pre-cut pads preferred)
• Thermal resistance target: <0.5°C/W

Mounting Torque:

1.4 Mechanical Mounting

Clearance Requirements:

Top: ≥10mm for airflow
Sides: ≥5mm for cable access
Bottom: ≥3mm for thermal pad
Rear: ≥20mm for connectors

Recommended Orientation:

• Heatsink fins oriented vertically for convection
• For forced air: airflow parallel to fins
• AvoidEnclosedenclosures without active cooling

1.5 Electrical Requirements

2. Reference Signal Input Configuration

2.1 Reference Input Specifications

2.2 Reference Source Requirements

Minimum Requirements:

2.3 Connection Diagram

┌─────────────────────────────────────────────────────────────┐
│ Typical System Configuration │
├─────────────────────────────────────────────────────────────┤
│ │
│ ┌─────────────┐ │
│ │ Reference │ 10 MHz @ +10 dBm │
│ │ Source │───────────────────┐ │
│ │ (Rubidium) │ │ │
│ └─────────────┘ │ BNC/SMA │
│ │ 50Ω │
│ ▼ │
│ ┌──────────────┐ │
│ │ REF INPUT │ │
│ │ SMA female │ │
│ └───────┬──────┘ │
│ │ │
│ ┌───────▼──────┐ │
│ │ │ │
│ │ PDRO Module │──────────────►│
│ │ │ RF Output │
│ │ │ (e.g., │
│ │ │ 6 GHz) │
│ └──────────────┘ │
│ │
│ DC Power: +12V to +28V @ 2A │
│ ┌─────────────┐ │
│ │ Power Supply│───────────────────────────────────────────│
│ └─────────────┘ │
└─────────────────────────────────────────────────────────────┘

2.4 Reference Input Configuration

Using Serial Interface (see datasheet for pinout):

*IDN?
> BRIDZA,STW-PDRO-S,SN-PD20240001,v1.2.0

:REF:SOURce?
> EXT10M

:REF:STATus?
> LOCKED

:REF:LEVel?
> 10.2 dBm

SCPI Reference Commands:

:REF:SOURce INT | EXT10M | EXT5M | EXT100M // Select reference
:REF:FREQuency? // Query reference freq
:REF:STATus? // Query lock status
:REF:LEVel? // Query input level
:REF:MODE NORmal | HUNT | ACQ // Lock mode

Lock Mode Selection:

2.5 Reference Cable Guidelines

Note: Use phase-stable cables for critical applications.

3. Phase Lock Status Monitoring

3.1 Lock Status Indicators

LED Indicators:

Status Register (via SCPI):

:STATus:OPERation?
> 257

// Bit 0: 1 = Locked
// Bit 1: 0 = No alarm
// Bit 8: 1 = Device operating

3.2 Monitoring via Serial Interface

Python Example:

import serial
import time

class BRIDZA_PDRO:
 def __init__(self, port='/dev/ttyUSB0'):
 self.serial = serial.Serial(port, 9600, timeout=1)
 
 def get_status(self):
 """Get comprehensive status"""
 status = {}
 
 # Lock status
 lock = self.command(':STATus:OPERation?')
 status['locked'] = bool(int(lock) & 1)
 
 # Alarm status
 alarm = self.command(':STATus:QUEStion?')
 status['alarm'] = bool(int(alarm) & 1)
 
 # Reference status
 ref_status = self.command(':REF:STATus?')
 status['ref_locked'] = (ref_status == 'LOCKED')
 
 # Temperature
 temp = self.command(':DIAG:TEMP?')
 status['temperature'] = float(temp)
 
 return status
 
 def wait_for_lock(self, timeout=30):
 """Wait for phase lock"""
 start = time.time()
 while time.time() - start < timeout:
 status = self.get_status()
 if status['locked']:
 return True
 time.sleep(0.5)
 return False
 
 def command(self, cmd):
 self.serial.write(f"{cmd}\n".encode())
 return self.serial.readline().decode().strip()
 
 def close(self):
 self.serial.close()

# Usage
pdro = BRIDZA_PDRO('/dev/ttyUSB0')
print("Waiting for lock...")
if pdro.wait_for_lock(timeout=60):
 print("LOCKED")
 print(pdro.get_status())
else:
 print("Lock timeout")
pdro.close()

3.3 Lock Quality Assessment

Monitor Lock Error Voltage (via D-SUB or ADC):

Interpretation:

• Error voltage near 2.5V = optimal lock
• Voltage drifting = approaching unlock
• Large swings = unstable reference

3.4 PLL Bandwidth Settings

For custom applications, PLL bandwidth may be adjustable:

// Set PLL bandwidth (if supported)
:PLL:BANDwidth 100 // 100 Hz bandwidth
:PLL:BANDwidth? // Query current bandwidth

// Set damping factor
:PLL:DAMPing 0.7 // 0.5 - 1.5 typical
:PLL:DAMPing?

Bandwidth Selection Guide:

4. RF Output Verification

4.1 RF Output Specifications

4.2 Output Verification Procedure

Equipment Required:

• Frequency counter (for frequency verification)
• Power meter or spectrum analyzer (for power verification)
• Phase noise analyzer (for PN verification)

Step 1: Frequency Verification

1. Connect frequency counter to RF output
2. Set counter to appropriate frequency range
3. Verify output frequency matches specification
4. Allow 5-minute warm-up, re-verify

Step 2: Power Verification

1. Connect power meter to RF output
2. Set meter to CW, 50Ω, appropriate frequency
3. Record output power
4. Verify within specification range

Step 3: Spectrum Verification

1. Connect spectrum analyzer to RF output
2. Set span to ±10% of center frequency
3. Verify:
 - Single carrier (no modulation)
 - No spurious signals > -60 dBc
 - No harmonics > -30 dBc
4. Save screenshot for documentation

4.3 Expected Performance Data

BRIDZA Typical Test Data:

Note: BRIDZA typical test data available upon request.

4.4 Output Matching Considerations

VSWR Optimization:

• PDRO output optimized for 50Ω load
• For non-50Ω systems, use matching network
• Verify with vector network analyzer

Power Variation with Load:

• Some power variation expected with different loads
• For critical applications, use buffer amplifier
• Maintain VSWR < 2:1 at all times

5. Troubleshooting

5.1 Lock Failure / Unlock Events

Diagnostic Flow:

1. Check POWER LED - should be green
2. Check LOCK LED - should be green (locked) or blinking (acquiring)
3. Measure reference input level - should be -10 to +13 dBm
4. Verify reference frequency - should match expected
5. Check module temperature - should be < 85°C
6. Power cycle and retry

5.2 Low Output Power

Diagnostic:

// Check output power (if supported)
:POW:RF?
> 11.5 dBm

// Check temperature
:DIAG:TEMP?
> 65.2

// Check lock status
:STAT:OPER?
> 257

5.3 Frequency Drift

Warm-Up Profile:

Time (min) | Frequency Error (ppm) | Power (dBm)
----------|------------------------|-------------
0 | ±5.0 | +8
5 | ±1.0 | +10
15 | ±0.5 | +11
30 | ±0.1 | +12
60 | ±0.01 | +12

5.4 Excessive Phase Noise

Diagnostic:

// Compare reference and output PN
:DIAG:PNOise? // If supported

// Check PLL parameters
:PLL:BANDwidth?
:PLL:DAMPing?

5.5 Communication Failure

Test Communication:

*IDN?
> BRIDZA,STW-PDRO-S,SN-PD20240001,v1.2.0

*VER?
> v1.2.0

Technical Support

For additional assistance:

• Email: [email protected]
• Documentation: https://rf.bridza.com/downloads
• Knowledge Base: https://rf.bridza.com/support

Document Version: 1.0 | Last Updated: 2025