SyncE — Synchronous Ethernet

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1. Definition

Synchronous Ethernet (SyncE) is a physical-layer frequency synchronization technology standardized by the ITU-T that enables the distribution of a highly accurate frequency reference over the existing Ethernet infrastructure. By transmitting a traceable clock signal embedded within the Ethernet bitstream, SyncE allows downstream network elements (NEs) to recover and lock to a common frequency reference — effectively transforming packet-based Ethernet networks into frequency-synchronous transport systems comparable to legacy SONET/SDH.

Unlike Precision Time Protocol (PTP / IEEE 1588), which operates at the packet layer and primarily delivers time-of-day (phase and time) synchronization, SyncE delivers frequency synchronization only. The two technologies are complementary: SyncE provides the stable frequency foundation upon which PTP can refine phase alignment.

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2. Technical Principles

2.1 Clock Recovery from Ethernet Bitstream

Traditional Ethernet is classified as plesiochronous — each node uses a free-running oscillator, and the physical layer coding (e.g., 8B/10B in 1000BASE-X, 64B/66B in 10GBASE-R) inherently absorbs small frequency offsets between transmitter and receiver via elastic buffers and comma alignment. SyncE leverages this property in reverse: by locking the transmit clock of an Ethernet port to a network reference, the recovered clock at the receiving port becomes a replica of that reference.

The process unfolds as follows:

  • **Reference injection**: A Synchronization Supply Unit (SSU) or Building Integrated Timing Supply (BITS) feeds a traceable clock (e.g., derived from GNSS or a primary reference clock) into an Ethernet Equipment Clock (EEC) within the line card or PHY.
  • **Physical-layer encoding**: The Ethernet PHY serializes data using this locked clock. The resulting line-rate signal inherently carries the frequency information — no additional signaling is required.
  • **Clock recovery at the far end**: The receiving PHY performs Clock and Data Recovery (CDR) from the incoming bitstream, extracting the embedded frequency reference.
  • **Loop filtering and holdover**: The recovered clock passes through a narrow-band digital phase-locked loop (DPLL) to filter jitter/wander, yielding a clean output for internal use or downstream distribution.
  • 2.2 Ethernet Synchronization Messaging Channel (ESMC)

    While the frequency reference is embedded in the bitstream, selection of the best timing source requires a signaling mechanism. This is provided by the ESMC (ITU-T G.8264), which uses slow protocol frames (EtherType 0x8809) to convey:

    | Field | Description |

    |-------|-------------|

    | QL (Quality Level) | SSM code indicating the quality/stratum of the clock source (e.g., QL-PRC, QL-SSU-A, QL-SSU-B, QL-SEC, QL-DNU) |

    | Event flags | Notification of holdover, failure, or source change |

    | Port state | Indicates whether a port is eligible for synchronization |

    Through ESMC, a network element running the Synchronization Selection Algorithm (SSA) can autonomously select the best available reference, switch sources upon degradation, and prevent timing loops — mirroring the well-known SSM (Synchronization Status Message) behavior of SONET/SDH.

    2.3 Ethernet Equipment Clock (EEC)

    The EEC is the local clock function within a SyncE-capable node. Its performance is defined in ITU-T G.8262 and comes in two options:

  • **EEC Option 1**: Aligned with SONET/SDH SEC (Stratum 3E equivalent) — pull-in range ±4.6 ppm, wander generation and tolerance per G.8262.
  • **EEC Option 2**: Optimized for environments also synchronized by 2048 kHz / 2 Mbit/s interfaces — compatible with SSU wander transfer characteristics.
  • The EEC must support free-run, locked, and holdover operating modes, with seamless transitions between them.

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    3. Key Parameters

    | Parameter | Typical Value / Requirement | Governing Standard |

    |-----------|---------------------------|---------------------|

    | Frequency accuracy (free-run) | ±4.6 ppm (Option 1) | G.8262 |

    | Holdover stability | ≤ 0.01 ppm/day aging (initial deviation ±0.01 ppm) | G.8262 |

    | Wander generation (MTIE/TDEV) | Per G.8262 masks | G.8262 |

    | Wander tolerance (input) | Per G.8262 masks; ≥ 18 µs MTIE tolerance | G.8262 |

    | Jitter tolerance | Per O.172 / G.8262 | G.8262 |

    | Jitter transfer bandwidth | 1–10 Hz typical (narrow-band) | G.8262 |

    | Pull-in / capture range | ±4.6 ppm (Option 1) | G.8262 |

    | ESMC message rate | 1 frame per second (default) | G.8264 |

    | QL codes supported | PRC, SSU-A, SSU-B, SEC, DNU (and equivalent) | G.8264 |

    MTIE (Maximum Time Interval Error) and TDEV (Time Deviation) are the primary wander metrics, computed from the phase difference between the recovered clock and the reference over observation windows ranging from 0.01 s to 1000 s.

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    4. Application Scenarios

    4.1 Mobile Backhaul and Fronthaul

    5G NR and LTE-Advanced base stations demand stringent frequency accuracy (±50 ppb for FDD carriers, ±0.05 ppm for fronthaul). SyncE delivers the frequency lock over Ethernet-based backhaul/fronthaul links, eliminating the need for dedicated TDM synchronization distribution.

    4.2 Carrier-Grade Ethernet and MPLS-TP

    Service provider networks transitioning from SONET/SDH to packet require SyncE to maintain timing traceability across Ethernet aggregation domains, ensuring jitter/wander budgets for circuit emulation (CES) and TDM-over-packet services.

    4.3 Data Center Interconnect (DCI)

    High-speed DCI links (100G/400G coherent optics) benefit from SyncE to synchronize line-side transponders, reducing framing errors and enabling deterministic performance in financial trading networks.

    4.4 Power Utility and Industrial Networks

    IEC 61850-based smart grid substations use SyncE to distribute a common frequency reference across Ethernet LANs, complementing IEEE 1588 for sub-microsecond time alignment of protection relays and merging units.

    4.5 GNSS-Denied Environments

    When GNSS is unavailable (indoor, jammed, or spoofed), SyncE can propagate a "golden clock" reference deep into the network via Ethernet, significantly reducing reliance on satellite timing.

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    5. Related Standards

    | Standard | Title | Scope |

    |----------|-------|-------|

    | ITU-T G.8261 | Timing and synchronization aspects in packet networks | Framework architecture; defines network limits for packet delay variation and synchronization |

    | ITU-T G.8262 | Timing characteristics of synchronous Ethernet equipment slave clock (EEC) | EEC performance requirements — wander, jitter, holdover |

    | ITU-T G.8264 | Distribution of timing information through packet networks | ESMC protocol specification; QL definitions |

    | ITU-T G.8263 | Characteristics of synchronous Ethernet equipment slave clock (EEC) for telecom boundary clock | Interaction between SyncE and PTP |

    | ITU-T G.781 | Synchronization layer functions | Architecture of synchronization networking for SDH/Ethernet hybrid |

    | ITU-T G.813 | Timing characteristics of SDH equipment slave clock (SEC) | Reference for EEC Option 1 alignment |

    | IEEE 802.3 | Ethernet standard | Physical-layer encoding mechanisms (8B/10B, 64B/66B, etc.) enabling CDR |

    | IEEE 1588-2019 | Precision Time Protocol (PTP) | Complementary time/phase synchronization; often deployed with SyncE |

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    6. Implementation Considerations & Product Context

    Implementing a robust SyncE subsystem in a network element or test platform demands:

  • **A high-performance DPLL** (typically a digital NCO-based architecture) capable of sub-Hz loop bandwidth to suppress incoming jitter while maintaining fast acquisition.
  • **Multi-reference selection logic** with ESMC-aware SSA, supporting revertive/non-revertive switchover and priority tables.
  • **Full MTIE/TDEV compliance monitoring** for real-time wander profiling against G.8262 masks.
  • **Holdover oscillators** (OCXO or DOCXO) with demonstrated aging stability to maintain accuracy during prolonged reference outages.
  • Modern synchronization test and measurement platforms — such as those offered by BRIDZA — provide integrated SyncE analysis capabilities including ESMC decode, QL monitoring, MTIE/TDEV mask compliance testing, and automated holdover characterization. These instruments are essential for verifying SyncE behavior during network commissioning, field troubleshooting, and vendor acceptance testing, particularly in complex multi-vendor environments where interoperability of EEC implementations must be validated against G.8262 and G.8264 conformance requirements.

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    7. Summary

    Synchronous Ethernet bridges the gap between the frequency-synchronous world of SONET/SDH and the packet-switched world of Ethernet. By embedding clock traceability at the physical layer and augmenting it with ESMC-based selection messaging, SyncE delivers carrier-grade frequency distribution without sacrificing the economics and flexibility of Ethernet. When combined with PTP for phase/time delivery, SyncE forms the frequency backbone of modern packet synchronization architecture — a cornerstone of 5G, smart grid, and deterministic networking deployments worldwide.

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    Keywords: SyncE, Synchronous Ethernet, ESMC, EEC, G.8262, G.8264, clock recovery, MTIE, TDEV, frequency synchronization, 5G timing