Phase Noise Budget: From Reference to Beam Pattern
AERIS-10 Phase Noise Budget Analysis
Application Note AN-AERIS-2025-003 Revision 1.0 — Phase Noise Budget for Coherent Radar Signal Processing
Table of Contents
1. Phase Noise Fundamentals 2. Budget Breakdown 3. Mathematical Analysis 4. Budget Allocation 5. BRIDZA Optimization 6. Measurement 7. References
1. Phase Noise Fundamentals
1.1 Definition and Physical Origin
Phase noise describes short-term, random frequency fluctuations in an oscillator signal. Any real oscillator output can be modeled as:
$$v(t) = \left[V_0 + \epsilon(t)\right] \cos\left[2\pi f_0 t + \phi(t)\right]$$
where $V_0$ is the nominal amplitude, $\epsilon(t)$ is amplitude noise, $f_0$ is the carrier frequency, and $\phi(t)$ is the random phase deviation. In practice, phase noise is far more consequential than amplitude noise because most receiver architectures employ limiters or AGC stages that suppress amplitude fluctuations, while phase fluctuations propagate unattenuated through the coherent processing chain.
Phase noise arises from fundamental thermal and shot noise processes in active devices, flicker (1/f) noise in semiconductor junctions, and environmental perturbations including vibration, temperature gradients, and power supply modulation. For the AERIS-10 coherent radar system, the spectral purity of every clock in the signal chain directly constrains achievable clutter cancellation, Doppler resolution, and beam pointing accuracy.
1.2 Single-Sideband Phase Noise Specification
The standard metric is single-sideband (SSB) phase noise, denoted $\mathscr{L}(f_m)$, defined as the ratio of noise power in a 1 Hz bandwidth at offset frequency $f_m$ from the carrier to the total carrier power:
$$\mathscr{L}(f_m) = \frac{P_{\text{sideband}}(f_0 + f_m, 1\text{ Hz BW})}{P_{\text{carrier}}} \quad [\text{dBc/Hz}]$$
The units dBc/Hz (decibels relative to the carrier per Hertz of bandwidth) encode both the magnitude and the spectral density nature of the quantity. A typical high-quality 10 MHz OCXO might exhibit:
| Offset (Hz) | Phase Noise (dBc/Hz) | |:---:|:---:| | 1 | −110 | | 10 | −135 | | 100 | −155 | | 1,000 | −160 | | 10,000 | −163 | | 100,000 | −165 |
Phase noise plots typically exhibit characteristic slope regions tied to noise mechanisms: $1/f^3$ (flicker FM), $1/f^2$ (random walk FM / white FM), $1/f$ (flicker PM), and flat (white PM) regions.
1.3 Relationship to Jitter
Phase noise and timing jitter are two representations of the same underlying phenomenon. The RMS phase jitter $\sigma_\phi$ (in radians) is obtained by integrating $\mathscr{L}(f_m)$ over the offset frequency band of interest:
$$\sigma_\phi^2 = 2 \int_{f_1}^{f_2} 10^{\mathscr{L}(f_m)/10} \, df_m \quad [\text{rad}^2]$$
The factor of 2 accounts for both sidebands (assuming symmetry). The corresponding RMS time jitter is:
$$\sigma_t = \frac{\sigma_\phi}{2\pi f_0} \quad [\text{seconds}]$$
For a 100 MHz clock with integrated phase noise of −45 dBc (i.e., $\sigma_\phi^2 = 10^{-4.5}$), the RMS phase deviation is approximately 0.1°, and the timing jitter is:
$$\sigma_t = \frac{0.00175 \text{ rad}}{2\pi \times 100 \times 10^6} \approx 2.8 \text{ ps RMS}$$
1.4 Why Phase Noise Matters in AERIS-10
The AERIS-10 architecture is a fully coherent, pulsed-Doppler system with stringent MTI (Moving Target Indication) requirements. Phase noise directly impacts:
- Clutter cancellation ratio (MTI improvement factor): Random phase variations between transmitted and received pulses decorrelate the clutter signal, limiting cancellation depth. - Doppler velocity accuracy: Phase noise broadens spectral lines, corrupting velocity estimation. - Beam pointing stability: In phased-array implementations, inter-channel phase coherence determines beam pointing accuracy and sidelobe levels. - ADC sampling integrity: The sampling clock's phase noise directly aliases into the digitized signal bandwidth.
A single corrupted clock can cascade through the entire system, making a rigorous phase noise budget essential.
2. Budget Breakdown
2.1 Reference Oscillator
The AERIS-10 reference oscillator is the ultimate phase noise source for the entire system. The BRIDZA subsystem provides the primary frequency reference. All downstream phase noise contributions are referenced to this source. Any noise at the reference propagates to every derived clock without attenuation (assuming ideal multiplication and distribution), making the reference oscillator the single most critical component in the budget.
For the AERIS-10, the reference operates at $f_{\text{ref}} = 100\text{ MHz}$, with the BRIDZA module providing an STW-OCXO or STM-Rb-N option depending on configuration.
2.2 PLL Multiplication Stage
The AD9523-1 PLL clock generator multiplies the 100 MHz reference to produce the required system clocks:
- ADC sample clock: $f_s = 1.0\text{ GHz}$ (×10 multiplication) - Digital signal processor clock: $f_{\text{DSP}} = 500\text{ MHz}$ (×5) - LO drive: $f_{\text{LO}} = 2.0\text{ GHz}$ (×20)
Phase noise degradation through a PLL multiplier follows:
$$\mathscr{L}_{\text{out}}(f_m) = \mathscr{L}_{\text{ref}}(f_m) + 20\log_{10}(N) + 10\log_{10}\left(\frac{f_{\text{vco,BW}}}{1\text{ Hz}}\right) \cdot \delta(f_m)$$
where $N$ is the multiplication factor and $f_{\text{vco,BW}}$ characterizes the VCO's contribution within its noise bandwidth. The term $20\log_{10}(N)$ is the multiplication penalty: a ×10 multiplier adds 20 dB to the reference phase noise at offset frequencies within the PLL loop bandwidth. Beyond the loop bandwidth, the VCO's free-running noise dominates.
The AD9523-1 with its integrated VCO typically achieves a closed-loop phase noise floor of approximately:
$$\mathscr{L}_{\text{PLL,floor}} \approx -155 \text{ dBc/Hz at } f_m = 100\text{ kHz (at 1 GHz output)}$$
2.3 Clock Distribution Network
The STW-DA16 distribution amplifier distributes the ADC sample clock to multiple ADC channels and provides additional outputs for the DSP subsystem. Distribution adds noise through:
- Additive phase noise floor of the distribution amplifier - Power supply noise coupling - Cable and PCB trace jitter accumulation (typically negligible at moderate lengths)
The STW-DA16 is characterized for ultra-low additive phase noise:
$$\mathscr{L}_{\text{DA16,floor}} \approx -165 \text{ dBc/Hz at } f_m = 100\text{ kHz (at 1 GHz)}$$
Since the distribution amplifier noise is uncorrelated with the PLL noise, the total output noise is the power sum:
$$\mathscr{L}_{\text{total}} = 10\log_{10}\left(10^{\mathscr{L}_{\text{PLL}}/10} + 10^{\mathscr{L}_{\text{DA16}}/10}\right)$$
2.4 ADC Sampling Clock
The ADC (assumed to be a high-speed SAR or pipeline converter at 1.0 GSPS) degrades signal SNR through aperture jitter $\sigma_{t,\text{ADC}}$. The SNR limit due to jitter alone for a full-scale sinusoidal input at frequency $f_{\text{in}}$ is:
$$\text{SNR}_{\text{jitter}} = -20\log_{10}\left(2\pi f_{\text{in}} \sigma_t\right) \quad [\text{dB}]$$
For the AERIS-10 at an intermediate frequency of $f_{\text{IF}} = 250\text{ MHz}$ with $\sigma_t = 100\text{ fs RMS}$:
$$\text{SNR}_{\text{jitter}} = -20\log_{10}\left(2\pi \times 250 \times 10^6 \times 100 \times 10^{-15}\right) = -20\log_{10}(1.57 \times 10^{-4}) \approx 76 \text{ dB}$$
This exceeds the ADC's inherent thermal SNR of approximately 70 dB (ENOB ≈ 11.3 bits), confirming that the sampling clock jitter is not the limiting factor in this configuration.
2.5 Total System Phase Noise Budget
The total integrated phase noise at the ADC input is the power sum of all uncorrelated contributions:
$$\mathscr{L}_{\text{sys}}(f_m) = \mathscr{L}_{\text{ref}}(f_m) + 20\log_{10}(N) \; \bigoplus \; \mathscr{L}_{\text{PLL,floor}}(f_m) \; \bigoplus \; \mathscr{L}_{\text{DA16,floor}}(f_m)$$
where $\bigoplus$ denotes power summation. The reference and multiplication terms are fully correlated (they represent the same noise source), while the PLL and distribution amplifier floor terms are uncorrelated with each other and with the reference.
3. Mathematical Analysis
3.1 Phase Noise to Beam Pattern Degradation
In the AERIS-10 phased-array architecture, each element $n$ receives a clock derived from a common reference but through individual distribution paths. The array factor for $N_{\text{el}}$ elements with ideal phase coherence is:
$$AF(\theta) = \sum_{n=0}^{N_{\text{el}}-1} A_n \exp\left[j\left(\frac{2\pi}{\lambda}nd\sin\theta + \phi_n\right)\right]$$
where $\phi_n$ represents the phase error at element $n$. When $\phi_n$ is a random variable with variance $\sigma_\phi^2$ derived from the phase noise budget, the expected beam gain is degraded. For small phase errors ($\sigma_\phi \ll 1$ rad):
$$E\left[|AF(\theta)|^2\right] = N_{\text{el}}^2 G_0(\theta) \cdot e^{-\sigma_\phi^2} + N_{\text{el}} \cdot (1 - e^{-\sigma_\phi^2})$$
where $G_0(\theta)$ is the normalized coherent beam pattern. The first term represents the coherent mainbeam, attenuated by $e^{-\sigma_\phi^2}$, while the second term represents incoherent power scattered into all directions (elevated sidelobes).
The peak gain loss in dB is:
$$\Delta G = 10\log_{10}\left(e^{-\sigma_\phi^2}\right) = -4.343 \, \sigma_\phi^2 \quad [\text{dB}]$$
For AERIS-10 with $N_{\text{el}} = 64$ elements, a peak gain loss of 0.1 dB requires:
$$\sigma_\phi^2 < \frac{0.1}{4.343} = 0.023 \text{ rad}^2 \implies \sigma_\phi < 0.152 \text{ rad} \approx 8.7°$$
The corresponding RMS sidelobe level from phase noise alone:
$$\text{SLL}_{\text{phase}} = \frac{1 - e^{-\sigma_\phi^2}}{N_{\text{el}} \cdot e^{-\sigma_\phi^2}} \approx \frac{\sigma_\phi^2}{N_{\text{el}}}$$
For $\sigma_\phi = 0.1$ rad and $N_{\text{el}} = 64$:
$$\text{SLL}_{\text{phase}} \approx \frac{0.01}{64} = 1.56 \times 10^{-4} = -38 \text{ dB}$$
This is well below the design sidelobe specification of −30 dB for the AERIS-10 antenna, confirming adequate margin.
3.2 MTI Improvement Factor Limitation
The MTI improvement factor $I_{\text{MTI}}$ for a two-pulse canceller limited by phase noise is:
$$I_{\text{MTI}} = \frac{1}{2(1 - \rho(\tau))}$$
where $\rho(\tau)$ is the autocorrelation function of the phase-noise-corrupted oscillator at the pulse repetition interval $\tau = 1/\text{PRF}$. For a first-order approximation with white FM noise:
$$\rho(\tau) \approx 1 - 2\pi^2 f_0^2 S_\phi(f) \cdot \Delta f_{\text{BW}} \cdot \tau$$
where $S_\phi(f)$ is the phase noise power spectral density integrated over the relevant offset bandwidth $\Delta f_{\text{BW}}$.
For the AERIS-10 operating at: - $f_0 = 10\text{ GHz}$ (X-band) - PRF = 10 kHz ($\tau = 100\,\mu\text{s}$) - Required MTI improvement: 50 dB
The maximum allowable integrated phase noise over the offset band 0 to PRF/2:
$$\sigma_\phi^2 < \frac{1}{2 \times 10^{I_{\text{MTI}}/10}} = \frac{1}{2 \times 10^5} = 5 \times 10^{-6} \text{ rad}^2$$
This corresponds to an RMS phase deviation of approximately 0.14° at the 10 GHz carrier. At the 100 MHz reference, the relaxed requirement is:
$$\sigma_{\phi,\text{ref}} = \frac{\sigma_{\phi,\text{carrier}}}{f_{\text{carrier}}/f_{\text{ref}}} = \frac{0.00245}{100} = 2.45 \times 10^{-5} \text{ rad}$$
This is an extremely tight constraint, emphasizing the necessity of a premium reference oscillator.
3.3 Doppler Impact Analysis
Doppler processing in AERIS-10 uses an $N_{\text{pulse}}$-pulse coherent processing interval (CPI). Phase noise within the CPI bandwidth corrupts Doppler estimation. The velocity estimation variance due to phase noise is:
$$\sigma_v^2 = \frac{c^2}{(2\pi f_0 T_{\text{CPI}})^2} \cdot \sigma_\phi^2$$
where $c$ is the speed of light, $f_0$ is the RF carrier frequency, and $T_{\text{CPI}} = N_{\text{pulse}} / \text{PRF}$ is the CPI duration.
For AERIS-10 with $N_{\text{pulse}} = 64$, PRF = 10 kHz:
$$T_{\text{CPI}} = 6.4 \text{ ms}$$
The Doppler resolution is:
$$\Delta f_D = \frac{1}{T_{\text{CPI}}} = 156.25 \text{ Hz}$$
Corresponding velocity resolution at 10 GHz:
$$\Delta v = \frac{c \cdot \Delta f_D}{2 f_0} = \frac{3 \times 10^8 \times 156.25}{2 \times 10 \times 10^9} = 2.34 \text{ m/s}$$
Phase noise causes spectral broadening of the clutter Doppler line. If the integrated phase noise over the CPI bandwidth introduces a phase variance of $\sigma_\phi^2$, the clutter line broadens, creating blind velocities and degrading minimum detectable velocity (MDV).
The clutter spectral width due to phase noise:
$$\sigma_{f,\text{clutter}} = \frac{\sigma_\phi}{2\pi T_{\text{CPI}}} = \frac{\sigma_\phi}{2\pi \times 6.4 \times 10^{-3}}$$
For $\sigma_\phi = 10^{-3}$ rad at the reference: $\sigma_{f,\text{clutter}} \approx 25$ mHz at the reference, scaling to 250 Hz at X-band — well within the clutter bandwidth from platform motion effects.
3.4 Integration Limits for Jitter Calculation
The practical integration range for jitter in the AERIS-10 system is bounded by:
- Lower limit: $f_1 = f_{\text{PRF}} / N_{\text{pulse}} = 10^4 / 64 \approx 156$ Hz. Below this, phase variations are common to all pulses within a CPI and cancel in MTI processing.
- Upper limit: $f_2 = f_s / 2 = 500$ MHz. Beyond Nyquist, phase noise is not sampled and does not affect the digital signal.
For the ADC jitter budget specifically, a tighter range is often used:
- Lower limit: 100 Hz (conventional offset) - Upper limit: Nyquist of the signal bandwidth
The integrated jitter is then:
$$\sigma_t = \frac{1}{2\pi f_0} \sqrt{2 \int_{f_1}^{f_2} 10^{\mathscr{L}(f_m)/10} \, df_m}$$
4. Budget Allocation
4.1 Where to Invest
The cascade of phase noise contributions follows a clear priority hierarchy. The power-sum relationship dictates that the largest contributor dominates the total. Investment in reducing a minor contributor while the dominant source remains unaddressed yields negligible system improvement.
For the AERIS-10, the budget contribution breakdown (at 100 kHz offset from a 1 GHz ADC clock) is:
| Source | Contribution (dBc/Hz) | % of Total Power | |:---|:---:|:---:| | Reference × 10 (via PLL) | −135 | 82% | | PLL floor (AD9523-1) | −155 | 8% | | Distribution (STW-DA16) | −165 | 3% | | ADC intrinsic | −170 | 2% | | Power supply / PCB | −168 | 5% | | Total | −133.5 | 100% |
This allocation clearly shows that the reference oscillator dominates, accounting for over 80% of total system phase noise power. Reducing the PLL floor or distribution amplifier noise by even 10 dB would improve the total by less than 0.5 dB.
4.2 Reference Priority
The $20\log_{10}(N)$ multiplication penalty makes the reference oscillator's phase noise the single most impactful parameter. For the AERIS-10's ×10 multiplication to the ADC clock:
$$\text{Penalty} = 20\log_{10}(10) = 20 \text{ dB}$$
Every 1 dB improvement in the reference oscillator's phase noise translates directly to a 1 dB improvement at every multiplied output — the only component in the system with this property. Therefore, the budget allocation philosophy for AERIS-10 is:
1. Maximize reference oscillator performance (highest return on investment) 2. Optimize PLL loop bandwidth to balance reference noise and VCO noise 3. Select low-floor distribution amplifiers (STW-DA16 is already near optimal) 4. Minimize power supply noise through proper filtering and regulation 5. Use ADC internal jitter as the residual floor (accept current ADC technology)
4.3 Practical Limits
Several practical constraints bound the optimization:
- Physical vibration sensitivity: Even the best OCXOs exhibit vibration-induced phase noise (acceleration sensitivity typically $10^{-9}$ to $10^{-10}$ per g). The AERIS-10 platform environment may require vibration isolation mounts.
- Temperature stability: The BRIDZA module operates over −40°C to +70°C. Phase noise at close-in offsets ($f_m < 10$ Hz) is sensitive to temperature fluctuations. An STM-Rb-N reference significantly outperforms an OCXO in this regime.
- Power consumption: Higher-performance oscillators consume more power. The STM-Rb-N requires approximately 1.5× the power of the STW-OCXO, a non-trivial consideration in the AERIS-10's power budget.
- Size and weight: The BRIDZA module must fit within the AERIS-10's allocated volume. Larger OCXO ovens provide better thermal isolation but increase form factor.
- Lock time: The PLL (AD9523-1) requires finite time to achieve lock after power-on. Cold-start lock time with an OCXO is typically 2–5 minutes; with a rubidium reference, 3–8 minutes. This constrains rapid deployment scenarios.
5. BRIDZA Optimization
5.1 STM-Rb-N Specifications
The STM-Rb-N (Spectratime miniaturized rubidium) provides the highest spectral purity available in the BRIDZA form factor. Key specifications relevant to the phase noise budget:
| Parameter | Value | |:---|:---| | Output frequency | 100 MHz | | Phase noise at 1 Hz | −100 dBc/Hz | | Phase noise at 10 Hz | −130 dBc/Hz | | Phase noise at 100 Hz | −148 dBc/Hz | | Phase noise at 1 kHz | −155 dBc/Hz | | Phase noise at 10 kHz | −158 dBc/Hz | | Phase noise at 100 kHz | −160 dBc/Hz | | Allan deviation (τ = 1 s) | $2 \times 10^{-12}$ | | Aging (per day) | $< 5 \times 10^{-12}$ | | Temperature coefficient | $< 3 \times 10^{-10}$ over −40 to +70°C | | Power consumption | 8 W (steady state) | | Warm-up time | < 5 min to lock | | Acceleration sensitivity | $< 2 \times 10^{-9}$ /g |
The STM-Rb-N's primary advantage is at close-in offsets (1–100 Hz), where the rubidium physics package provides an inherently stable frequency reference that no crystal oscillator can match. This directly benefits the MTI improvement factor, which is most sensitive to phase noise at offsets near the PRF and its harmonics.
5.2 STW-OCXO Comparison
The STW-OCXO option provides excellent performance with lower power consumption and faster warm-up:
| Parameter | STW-OCXO | STM-Rb-N | Advantage | |:---|:---:|:---:|:---:| | Phase noise at 1 Hz | −90 dBc/Hz | −100 dBc/Hz | Rb: 10 dB | | Phase noise at 10 Hz | −125 dBc/Hz | −130 dBc/Hz | Rb: 5 dB | | Phase noise at 100 Hz | −150 dBc/Hz | −148 dBc/Hz | OCXO: 2 dB | | Phase noise at 1 kHz | −160 dBc/Hz | −155 dBc/Hz | OCXO: 5 dB | | Phase noise at 10 kHz | −165 dBc/Hz | −158 dBc/Hz | OCXO: 7 dB | | Allan deviation (1 s) | $5 \times 10^{-12}$ | $2 \times 10^{-12}$ | Rb: 2.5× | | Power consumption | 3 W | 8 W | OCXO: 2.7× | | Warm-up time | < 2 min | < 5 min | OCXO: 2.5× |
The comparison reveals an important crossover: the STW-OCXO has superior phase noise at offsets above ~200 Hz, while the STM-Rb-N dominates below 200 Hz. This crossover frequency is critical for system design:
- For MTI-dominated applications (where close-in phase noise at offsets of 10–1000 Hz determines clutter cancellation), the STM-Rb-N is preferred. - For wideband ADC-dominated applications (where far-out phase noise at offsets >10 kHz determines sampling jitter), the STW-OCXO is preferred. - For the AERIS-10 general-purpose configuration, the STM-Rb-N is recommended because MTI performance is typically the limiting system requirement.
5.3 STW-DA16 Noise Floor
The STW-DA16 distribution amplifier is designed for ultra-low additive noise. Its key characteristics:
- Additive phase noise floor: −165 dBc/Hz at 100 kHz offset (for 1 GHz output) - Output-to-output isolation: > 60 dB - Skew adjustment range: ±5 ns with 1 ps resolution - Number of outputs: 16 (configurable as differential LVPECL or LVDS) - Power supply rejection ratio (PSRR): > 40 dB at 100 kHz
The STW-DA16 achieves its noise floor through several design choices:
1. Differential signal paths throughout, rejecting common-mode power supply noise 2. Internal low-noise LDO regulators with dedicated analog and digital supply domains 3. Short, matched internal trace lengths minimizing group delay variation 4. Output buffer stages with optimized bias current for minimum noise figure
The STW-DA16's noise floor of −165 dBc/Hz is approximately 10 dB below the PLL output noise and 30 dB below the multiplied reference noise, confirming that distribution is not a significant contributor to the AERIS-10 phase noise budget.
Optimization recommendation: In configurations where multiple BRIDZA modules distribute clocks across large arrays, the STW-DA16's skew adjustment capability enables sub-picosecond channel-to-channel alignment, critical for maintaining beam pointing accuracy without consuming phase noise budget margin.
6. Measurement
6.1 Phase Noise Measurement Setup
Validating the AERIS-10 phase noise budget requires measurement at multiple points in the signal chain. The recommended measurement topology uses the cross-correlation phase noise measurement technique, which achieves measurement floors well below the noise of any single reference source.
Equipment list:
1. Phase noise analyzer: Keysight E5052B or Rohde & Schwarz FSWP 2. Low-noise reference source: Second BRIDZA module (same configuration as DUT) or dedicated ultra-low-noise OCXO 3. Frequency down-converter: For measuring the 2 GHz LO drive output 4. Spectrum analyzer: For wideband verification (Keysight N9040B or equivalent) 5. Vibration isolation table: For eliminating environmental acoustic noise during close-in measurements
Measurement procedure for the reference oscillator:
BRIDZA DUT ──► Phase Input A ──┐
├──► E5052B Cross-Correlator
BRIDZA REF ──► Phase Input B ──┘
The cross-correlation technique processes $M$ independent correlations of the DUT and REF signals. The measurement floor improves as:
$$\mathscr{L}_{\text{meas,floor}} = \mathscr{L}_{\text{DUT}} - 10\log_{10}(M) + 3 \text{ dB}$$
For $M = 100$ correlations, the effective measurement floor drops by 20 dB relative to a single measurement. This is essential for validating the STM-Rb-N specification of −160 dBc/Hz at 100 kHz offset, which requires a measurement floor below approximately −165 dBc/Hz.
6.2 Measurement Points and Procedures
The complete validation requires measurements at six points:
| Test Point | Signal | Equipment | Key Metric | |:---|:---|:---|:---| | TP1 | BRIDZA 100 MHz output | E5052B cross-correlation | Reference PN | | TP2 | AD9523-1 output (1 GHz) | E5052B + prescaler | PLL PN at ×10 | | TP3 | STW-DA16 output (1 GHz) | E5052B additive PN mode | Distribution PN | | TP4 | ADC sample clock input | Residual PN measurement | Total clock PN | | TP5 | ADC digital output | Digital PN extraction | ADC-inclusive PN | | TP6 | LO drive (2 GHz) | FSWP down-conversion | LO PN |
Test Point 2 (PLL validation):
The AD9523-1 output phase noise is measured against the second BRIDZA reference, with both locked to a common 10 MHz GPS-disciplined reference for frequency offset removal. The measured phase noise should match the predicted value:
$$\mathscr{L}_{\text{predicted}}(f_m) = 10\log_{10}\left(10^{\mathscr{L}_{\text{ref}}(f_m)/10 + 20\log_{10}(N)/10} + 10^{\mathscr{L}_{\text{PLL}}(f_m)/10}\right)$$
6.3 Validation Criteria
The AERIS-10 phase noise budget defines pass/fail criteria at each test point:
| Test Point | Frequency | Offset | Requirement (dBc/Hz) | Margin | |:---|:---:|:---:|:---:|:---:| | TP1 | 100 MHz | 10 Hz | ≤ −128 | 2 dB | | TP1 | 100 MHz | 1 kHz | ≤ −153 | 2 dB | | TP1 | 100 MHz | 100 kHz | ≤ −158 | 2 dB | | TP2 | 1 GHz | 10 kHz | ≤ −135 | 3 dB | | TP2 | 1 GHz | 100 kHz | ≤ −138 | 3 dB | | TP4 | 1 GHz | 1 kHz | ≤ −130 | 3 dB | | TP4 | 1 GHz | 100 kHz | ≤ −133 | 3 dB |
Margin values include allowances for temperature variation (±1 dB), vibration (±1 dB), and aging (±1 dB).
6.4 Common Measurement Pitfalls
Power supply contamination: Switching regulators introduce spurious tones that appear as discrete spurs in the phase noise spectrum, not broadband noise. Always measure with linear regulators during validation and characterize supply sensitivity separately.
Microphonic effects: Even on vibration isolation tables, acoustic coupling from HVAC systems can contaminate measurements below 1 kHz offset. Perform close-in measurements in a controlled acoustic environment or use time-gated measurement techniques.
Reference oscillator contamination: In cross-correlation measurements, insufficient correlation averaging ($M$ too small) leaves residual reference noise in the measurement. Verify convergence by monitoring the measured noise level as $M$ increases.
Connector repeatability: Phase noise measurements at the −160 dBc/Hz level require gold-plated, precision 3.5 mm or 2.92 mm connectors. Torque wrenches must be used consistently (8 in·lbf for 3.5 mm).
Cable phase stability: Semi-rigid cables should be used for all measurement connections. Flexible cables introduce microphonic phase modulation that appears as elevated close-in phase noise.
7. Summary
The AERIS-10 phase noise budget is dominated by the BRIDZA reference oscillator, which contributes over 80% of the total system phase noise through the ×10 PLL multiplication to the 1 GHz ADC clock. The STM-Rb-N option provides 5–10 dB improvement over the STW-OCXO at critical close-in offsets (1–200 Hz), directly benefiting MTI improvement factor and beam pointing stability.
Key design rules derived from this analysis:
1. Invest in the reference first. Every 1 dB of improvement at the 100 MHz reference translates to 1 dB at every system clock. 2. Set PLL loop bandwidth at the crossover between reference noise (×N²) and VCO free-running noise — typically 100–500 kHz for the AD9523-1 with STW-OCXO reference. 3. The STW-DA16 distribution amplifier is not a limiting factor — its −165 dBc/Hz floor is well below all other contributors. 4. ADC jitter is adequate for the 12-bit conversion requirement with current clock performance. 5. Validate at multiple points in the signal chain; total-system jitter measurements alone cannot identify the dominant contributor.
The integrated system phase noise of −133.5 dBc/Hz at the ADC clock (100 kHz offset) provides adequate margin for the AERIS-10's 50 dB MTI improvement specification and −30 dB sidelobe level requirement.
8. References
1. E. Rubiola, Phase Noise and Frequency Stability in Oscillators, Cambridge University Press, 2008. 2. W. P. Robins, Phase Noise in Signal Sources, IEE Telecommunications Series, 1982. 3. A. Hati, D. A. Howe, F. L. Walls, "Noise Figure vs. PM Noise Measurements: A Study at Microwave Frequencies," IEEE Trans. UFFC, 2003. 4. Analog Devices, "AD9523-1: 14-Output, Low Jitter Clock Generator," Datasheet Rev. C, 2019. 5. M. I. Skolnik, Introduction to Radar Systems, 3rd ed., McGraw-Hill, 2001. 6. Spectratime (STM), "STM-Rb-N Miniature Rubidium Frequency Standard," Product Specification, 2023. 7. STW Technische Produkte, "STW-DA16 Ultra-Low Noise Clock Distribution Amplifier," Datasheet, 2024. 8. STW Technische Produkte, "STW-OCXO High-Stability Oven Controlled Crystal Oscillator," Datasheet, 2024.
© 2025 — AERIS-10 System Engineering Group. All rights reserved. This application note is provided for technical reference purposes. Specifications are subject to change. Contact the system engineering team for application-specific guidance.
Document Control: - AN-AERIS-2025-003 Rev 1.0 - Classification: Technical — Unrestricted - Keywords: phase noise budget, AERIS-10, beam pattern, MTI, AD9523-1, BRIDZA, STM-Rb-N, STW-OCXO, STW-DA16, jitter, Doppler, clock distribution