AERIS-10 Timing Upgrade Kit: Adding BRIDZA STM-Rb-N

Application Note | BRIDZA

Application Note: Upgrading the AERIS-10 Radar Timing System with the BRIDZA STM-Rb-N Rubidium Oscillator

Document Number: AN-AERIS10-RB-001 Revision: 1.0 Target System: AERIS-10 Multimode Surveillance Radar Upgrade Kit: BRIDZA STM-Rb-N Precision Timing Module Keywords: AERIS-10 timing upgrade, BRIDZA STM-Rb-N, rubidium upgrade, radar coherence, phase noise, AD9523-1

1. Kit Overview

1.1 Purpose

This application note provides a comprehensive guide for upgrading the AERIS-10 radar's master timing generator from its standard Temperature Compensated Crystal Oscillator (TCXO) to the high-stability BRIDZA STM-Rb-N Rubidium Oscillator Module. This upgrade is critical for applications requiring: * Longer coherent integration times (CIT) for improved detection of slow-moving or stealthy targets. * Enhanced Doppler resolution and clutter rejection. * Superior radar-to-radar time synchronization in multistatic or networked radar systems. * Phase-coherent operation over extended periods and across wide temperature ranges.

The BRIDZA STM-Rb-N provides the necessary frequency stability and phase noise performance to unlock the full potential of the AERIS-10's advanced signal processing algorithms.

1.2 Upgrade Kit Contents (P/N: AERIS10-RB-KIT-01)

* 1x BRIDZA STM-Rb-N Rubidium Oscillator Module (P/N: STM-Rb-N-10M) * 1x Precision Mounting Bracket & Thermal Isolation Pad Kit * 1x RF Cable Assembly, SMA-M to SMA-M, 0.86mm SS405, 24" (low-loss, phase-stable) * 1x DC Power Harness with filtered connectors (for +12V and +5V rails) * 1x Configuration & Status Cable (10-pin header to DB-9) * 1x USB-to-Serial Adapter for initial module configuration * 1x Application Note & Quick Start Guide (this document)

1.3 BRIDZA STM-Rb-N Specifications (Key Parameters)

1.4 AERIS-10 Compatibility

The upgrade kit is designed for direct compatibility with: * AERIS-10 Processing Unit (PPU) Rev. 3.2 and later. * Timing Generator Card (TGC) assembly P/N: AERIS10-TGC-V2. * The system's existing AD9523-1 clock distribution IC (located on the TGC). The STM-Rb-N's 10 MHz output directly replaces the 10 MHz TCXO reference. No hardware modifications to the TGC are required for signal routing. * Firmware Requirement: AERIS-10 System Firmware v5.4.1 or later. This version includes the required drivers and control logic for external rubidium references. Verify the firmware version via the System Control Console (sysctl --version) before proceeding.

2. Prerequisites

2.1 Tools and Equipment Required

* ESD-Safe Workstation: Wrist strap, mat, and proper grounding. * Tool Kit: #2 Phillips screwdriver, 2.5mm hex key, 5/16" nut driver, needle-nose pliers, wire cutters/strippers. * Multimeter: For verifying DC voltages. * Oscilloscope: 100 MHz bandwidth minimum, with 50Ω input capability, for initial signal verification. * Spectrum Analyzer: With phase noise measurement capability (optional but recommended for final verification). * Laptop/PC: With terminal emulator (e.g., PuTTY, minicom) and DB-9 serial port (or USB-Serial adapter).

2.2 Safety Considerations

1. POWER DOWN: Disconnect all AC and DC power from the AERIS-10 system cabinet. Verify power is off by observing indicator LEDs and checking with a multimeter at the main power entry. 2. LOCKOUT/TAGOUT (LOTO): Implement site-specific LOTO procedures to prevent accidental re-energization. 3. HIGH VOLTAGE: The AERIS-10 transmitter (HVE) and power supplies contain high-voltage capacitors. Do not open transmitter enclosures. This upgrade is confined to the receiver/exciter (REX) and processor (PPU) units. 4. RF HAZARD: Ensure the radar is in a safe, non-transmitting state. Post "RF Hazard - Maintenance in Progress" signage. 5. HEAVY EQUIPMENT: The AERIS-10 cabinet is heavy. Use appropriate lifting techniques or mechanical aids.

2.3 System Backup and Documentation

1. Record Existing Configuration: * From the System Control Console, run: timing --showconfig > /backup/timing_config_preupgrade.txt * Note the current firmware version: sysctl --version > /backup/firmware_version.txt 2. Backup Software: Create a full system software backup using the provided backup utility: sysbackup --full --dest /external_usb/ 3. Photograph Everything: Take clear, labeled photos of the Timing Generator Card (TGC) before disassembly, showing all cable connections, jumper settings (JP1-JP4), and the orientation of the existing TCXO module. 4. Verify Kit Contents: Unpack the upgrade kit and verify all components against the packing list in Section 1.2.

3. Installation Procedure

3.1 Physical Mounting

Objective: Securely install the BRIDZA STM-Rb-N in an optimal location within the PPU chassis, ensuring good thermal stability and minimal vibration.

1. Locate Mounting Area: Identify the pre-drilled mounting holes on the internal chassis plate, adjacent to the TGC. This area is designed for optional high-stability oscillators. 2. Install Thermal Pad: Clean the mounting surface with isopropyl alcohol. Apply the provided adhesive-backed thermal isolation pad to the chassis plate. 3. Mount the Module: * Place the BRIDZA STM-Rb-N onto the thermal pad. * Secure the module using the provided M3 screws and the mounting bracket. Torque screws to 0.6 Nm (finger-tight plus 1/4 turn). Over-torquing can damage the module's enclosure. * Ensure the module's status LEDs and the RS-232 header are accessible.

3.2 RF Connection

Objective: Replace the TCXO reference signal path with the BRIDZA STM-Rb-N's output.

1. Disconnect Old Reference: On the TGC, locate the coaxial cable connected to J4 (labeled TCXO_OUT or REF_IN). Carefully disconnect it. 2. Connect New Reference: * Connect the provided SMA-M to SMA-M cable from the BRIDZA STM-Rb-N's RF OUT port. * Route the cable neatly along the chassis and connect the other end to J4 on the TGC. * Do not over-tighten SMA connectors. Use a 5/16" wrench, tighten to 0.5 Nm.

3.3 Power Connections

Objective: Provide clean, stable DC power to the rubidium module.

1. Locate Power Source: On the PPU's main power distribution board (PDB), locate the spare filtered power headers: J-PWR-SPARE1 (+12V) and J-PWR-SPARE2 (+5V). These are enabled by default. 2. Connect Power Harness: * RED: +12V to J-PWR-SPARE1 (Pin 1: +12V, Pin 2: GND). * ORANGE: +5V to J-PWR-SPARE2 (Pin 1: +5V, Pin 2: GND). * BLACK: Connect the harness ground lugs to the chassis grounding stud using the provided star washer. 3. Secure Cables: Use provided cable ties to route and secure all new cables, preventing contact with fans or other moving parts.

3.4 AD9523-1 Configuration & Status Cable

Objective: Enable communication between the BRIDZA module and the AERIS-10 system for status monitoring and lock detection.

1. Connect Status Cable: * Plug the 10-pin connector into the STATUS/CTRL header on the BRIDZA STM-Rb-N. * Connect the DB-9 end to the EXT REF STATUS port (P2) on the TGC. 2. AD9523-1 Jumper Settings (TGC): * JP1: Move jumper from 2-3 (TCXO) to 1-2 (EXT Rb). This routes the 10 MHz from J4 to the AD9523-1's reference input. * JP2: Set to 1-2 (PLL Loop BW: NARROW). This optimizes the AD9523-1's PLL for locking to a high-stability reference. * JP3 & JP4: Leave in default positions (1-2).

3.5 Initial Power-Up and Lock Verification

CAUTION: Double-check all connections before applying power.

1. Apply Power: Reconnect main AC/DC power to the AERIS-10 system. Do not enable transmitter. 2. Observe Module LEDs: * PWR (Green): Should illuminate within 1 second. * LOCK (Yellow/Amber): Will blink during warm-up (approx. 2-5 minutes), then turn STEADY GREEN when frequency lock is achieved. 3. Verify with Oscilloscope (if available): * Set scope to 50Ω input, 10 MHz/div, 100mV/div. * Probe the test point TP1 on the TGC, labeled 10MHz_REF. * Verify a clean 10 MHz sinewave with an amplitude of approximately 1.4 Vpp (0 dBm into 50Ω).

4. System Configuration

4.1 Software Configuration for External Reference

Once the hardware is installed and the BRIDZA module shows a steady green LOCK LED, configure the AERIS-10 software.

1. Access System Control Console via the main operator terminal. 2. Enable External Rubidium Reference:

 sysctl --set timing.reference=EXT_RUBIDIUM
 sysctl --set timing.ref_mode=ACTIVE

3. Verify Reference Status:

 sysctl --query timing.reference_status

Expected Output:

 External Reference: PRESENT
 Lock Status: LOCKED
 Module: BRIDZA STM-Rb-N
 Frequency Offset: < 5e-12

4.2 Clock Rate Programming (Optional Fine-Tuning)

For advanced applications, the master clock rate derived from the 10 MHz reference can be fine-tuned.

1. View Current Clock Distribution:

 timing --showclocks

2. Adjust System Clock (if necessary): * The default system clock is 100.000000 MHz (10 MHz x 10). * To micro-adjust for phase alignment in a multi-radar system:

 timing --adjust clock_100mhz --offset 
 # Example: timing --adjust clock_100mhz --offset +0.005

* Changes are applied instantly to the AD9523-1 registers. Use with caution.

4.3 Final Configuration Verification

Perform a system-wide timing check to ensure all sub-systems are synchronized to the new reference.

timing --selftest --verbose

This test will: 1. Confirm the 10 MHz reference lock. 2. Verify the integrity of all derived clocks (100 MHz, 250 MHz, etc.). 3. Run a brief phase noise analysis on internal loop-back. All test results must be PASS. If any test fails, refer to the Troubleshooting section.

5. Performance Verification

5.1 Phase Noise Measurement

Objective: Quantify the improvement in close-in phase noise, which directly impacts radar coherence.

Procedure: 1. Connect the spectrum analyzer to TP1 on the TGC via a 20 dB attenuator (to protect the analyzer). 2. Set the analyzer: Center Freq = 10 MHz, Span = 1 kHz, RBW = 10 Hz, VBW = 10 Hz. 3. Enable the Phase Noise measurement function. 4. Measure and record the noise at the following offsets: * @ 10 Hz offset: Should be ≤ -110 dBc/Hz. * @ 100 Hz offset: Should be ≤ -130 dBc/Hz. * @ 1 kHz offset: Should be ≤ -145 dBc/Hz. 5. Compare these results to the factory specification sheet. The measured values should be within 3 dB of the nominal specs.

5.2 Coherent Integration Time (CIT) Test

Objective: Demonstrate the practical benefit of the upgrade by increasing the system's CIT.

Test Setup: * Point the AERIS-10 at a stationary, strong point target (e.g., a corner reflector at 5 km). * Use the standard weather clutter environment.

Procedure: 1. Baseline (with old TCXO - reference data): * Set CIT to 50 ms. Note the signal-to-clutter ratio (SCR) of the target. * Increase CIT in steps. The SCR will degrade noticeably beyond ~100-200 ms due to TCXO phase drift. 2. Post-Upgrade Test: * Repeat the CIT sweep. * With the BRIDZA STM-Rb-N, the SCR should remain stable and continue to improve with longer CITs up to 2-5 seconds. * Expected Result: A 3-6 dB improvement in minimum detectable velocity (MDV) and clutter rejection for slow targets. Record the new maximum usable CIT.

5.3 Frequency Accuracy Verification

Objective: Confirm the long-term stability of the reference.

1. Use a frequency counter with a known GPS-locked reference. 2. Measure the frequency of TP1 over a 24-hour period, sampling every minute. 3. Calculate the Frequency Accuracy (Δf/f) and Allan Deviation at τ=1s, τ=10s, and τ=100s. 4. Expected Result: Frequency accuracy should be < 1 x 10⁻¹⁰ after 24h warm-up. Allan Deviation at τ=1s should be < 2 x 10⁻¹², matching the module spec.

6. Troubleshooting

6.1 Common Issues and Solutions

| Symptom | Possible Cause | Solution | | :--- | :--- | :--- | | BRIDZA LOCK LED never turns solid green. | 1. Insufficient warm-up time.
2. Power supply issue.
3. Faulty module. | 1. Wait 10 minutes in a stable environment.
2. Verify +12V (11.5-12.5V) and +5V (4.75-5.25V) at the module's power connector.
3. Cycle power. If persists, contact support. | | System reports TIMING_REF_UNLOCK alarm. | 1. RF cable loose or damaged.
2. TGC jumper JP1 not set correctly.
3. AD9523-1 PLL not locked. | 1. Reseat SMA connectors. Test cable continuity.
2. Confirm JP1 is on pins 1-2.
3. Run timing --selftest. If PLL fails, power cycle system. | | Poor phase noise measurement. | 1. Test setup issue (ground loop, bad cable).
2. Environmental vibration.
3. RF interference. | 1. Verify analyzer calibration, use short, quality cables, ensure single-point grounding.
2. Check mounting tightness. Isolate module from high-vibration sources (fans).
3. Move test to a shielded room if possible. | | timing --selftest fails. | 1. Firmware version too old.
2. Configuration command not applied.
3. TGC hardware fault. | 1. Verify firmware v5.4.1+. Upgrade if needed.
2. Re-run sysctl --set timing.reference=EXT_RUBIDIUM.
3. Inspect TGC for damaged components or solder bridges. | | Frequency counter shows large offset (>1 Hz). | Module needs re-calibration or is in a severe thermal gradient. | Allow 72-hour burn-in. If offset persists, use the serial interface to apply a frequency correction: SYST:CORR:FREQ via a terminal program. |

6.2 Technical Support

For issues not resolved by this guide, please contact: * BRIDZA Technical Support: For module-specific issues (lock, power, communications). * AERIS-10 Field Service: For system integration, TGC, or firmware issues. Provide the following with any service request: 1. Output of sysctl --query timing.reference_status. 2. Output of timing --selftest --verbose. 3. Photographs of the installation. 4. Description of observed symptoms and steps already taken.

Document End. This upgrade, when performed correctly, will provide your AERIS-10 radar with a foundational stability that enables next-generation detection performance. Regularly schedule annual verification checks to ensure optimal long-term operation.

← Back to AERIS-10 Index